Multi-processing systems utilize multiple processors (e.g., central processing units (CPU)) to process data and perform desired functions. As will be appreciated, the term “processor” is used synonymously with the terms “CPU” or “core” and is readily understood by those skilled in the art. In the prior art, there exist two main types of disparate multi-processing systems: Symmetric multi-processing (SMP) and asymmetric multi-processing (ASMP).
SMP systems are typically characterized by the sharing of all system resources, a single synchronous L2 cache interface (and possibly asynchronous L2), processors are controlled at the same clock frequency and clock voltage. This also general means the processors/cores are equally accessible to the shared memory system (such as L2 cache and memory). In SMP, clock frequencies and voltages are not individually adjustable and, therefore, cannot be changed on a per core/processor basis. In addition, the L2 cache is shared among all cores and the L2 cache frequency is not scalable on a per core basis. In most, if not all applications, workloads of the processors in SMP are unbalanced and this leads to higher power consumption.
In contrast, ASMP systems are typically characterized by having different clock frequencies and/or clock voltages individually for processors and the L2 cache clock frequency can be independently scaled. Thus, processor clock frequency and L2 cache frequency can be scaled based on workload (e.g., faster L2 cache relative to cores for memory intensive workloads). In general terms, ASMP systems are more power efficient than SMP systems, but potentially higher power consumption may be caused by the additional and more complex hardware. When the L1 cache miss rate is high, the processor will fetch date from the L2 cache. If the requested relevant data is stored in the lower clock frequency portion of the L2 cache, the processor has to wait for the data. This leads to higher latency and higher power consumption.
Turning to FIG. 1, there is illustrated the basic architecture of a processing system 100 having multiple processors employing ASMP. As will be appreciated, a similar prior art system is utilized for SMP, however, the processors operate at a single clock frequency and using a single supply voltage level—as readily understood by persons of ordinary skill in the art.
The processing system 100 includes a multi-processor cores and caches subsystem 105 having multiple processors 110 (110a, 110b, 110c, 110d) with corresponding L2 cache memory portions 120 (120a, 120b, 120c, 120d) and clock domain crossing (CDC) circuits 130 (130a, 130b, 130c, 130d), as illustrated. Though four processors 110 (and corresponding memory and circuitry) are shown, the number of processors could be fewer or greater, but will include at least two. As will be appreciated, each processor 110 may include one or more central processing units (CPUs).
The processing system 100 further includes a power management control (PMIC) circuit 140 for generating multiple supply voltage signals for use in supplying power to the respective processors, caches and CDCs. Similarly, a clock generation circuit 150 generates multiple clock signals having various predetermined clock frequencies for use in clocking operation of the respective processors, caches and CDCs. As will be appreciated, the PMIC circuit may be on the same substrate as the subsystem 105 or may be provisioned on another substrate (e.g., in another IC).
As noted above and readily understood by those skilled in the art, each of the distinct SMP and ASMP architectures/systems have various advantages or benefits, as well as various disadvantages or drawbacks. Due to the complexity and costs for each type of system (both in hardware and software functionality), a designer typically must choose either the SMP system or the ASMP system based on the particular application(s).
Accordingly, there is needed a multiprocessing system or architecture that can operate and provide the functionality of both an SMP system and an ASMP system without having duplicate multi-processor cores, caches and CDC subsystems. There is also needed a method for control and selection of either the SMP or ASMP mode to reduce power consumption and increase efficiency.